Biagio Peccerillo

Researcher
Institute of Science and Technologies
"A. Faedo" (ISTI)
National Research Council of Italy (CNR)

Contacts

biagio.peccerillo@isti.cnr.it
peccerillo@diism.unisi.it

Publications

Legend:
Journal Conference Book Chapter Other

2025

[21] High-Performance Multi-Object Tracking for Autonomous Driving in Urban Scenarios with Heterogeneous Embedded Boards
A. Medaglini, B. Peccerillo, S. Bartolini.
IEEE Access 13, 2025, pp. 8649-8663.
ACCESS

2024

[20] DeVAS: Decoupled Virtual Address Spaces
M. Mannino, B. Peccerillo, A. Mondelli, S. Bartolini.
Proceedings of the IEEE 36th International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD), Hilo, USA, 2024, pp. 182-193.
SBAC-PAD

[19] MORUS-PRNG: a Hardware Accelerator Based on the MORUS Cipher and the IXIAM Framework
A. Medaglini, M. Mannino, B. Peccerillo, S. Bartolini.
Proceedings of the 18th International Conference on Advanced Engineering Computing and Applications in Sciences (ADVCOMP 2024), Venice, Italy, 2024, pp. 1-7.
ADVCOMP

[18] Accelerating Differential Privacy-Based Federated Learning Systems
M. Mannino, A. Medaglini, B. Peccerillo, S. Bartolini.
Proceedings of the 18th International Conference on Advanced Engineering Computing and Applications in Sciences (ADVCOMP 2024), Venice, Italy, 2024, pp. 8-10.
ADVCOMP

[17] Integration of RISC-V Page Table Walk in gem5 SE Mode
M. Mannino, Y. Huang, B. Peccerillo, A. Medaglini, S. Bartolini.
Proceedings of the 16th Workshop on Rapid Simulation and Performance Evaluation for Design Optimization: Methods and Tools (RAPIDO'24), Munich, Germany, 2024, pp. 22-28.
RAPIDO

2023

[16] Analysis and Optimization of Direct Convolution Execution on Multi-Core Processors
M. Mannino, B. Peccerillo, A. Mondelli, S. Bartolini.
IEEE Access 11, 2023, pp. 57514-57528.
ACCESS

[15] Energy and Performance Improvements for Convolutional Accelerators Using Lightweight Address Translation Support
M. Mannino, B. Peccerillo, A. Mondelli, S. Bartolini.
Proceedings of the 20th ACM International Conference on Computing Frontiers 2023 (CF 2023), Bologna, Italy, 2023, pp. 84-90.
CF 2023

[14] IXIAM: ISA EXtension for Integrated Accelerator Management
B. Peccerillo, E. Cheshmikhani, M. Mannino, A. Mondelli, S. Bartolini.
IEEE Access 11, 2023, pp. 33768-33791.
ACCESS

2022

[13] A General Framework for Accelerator Management Based on ISA Extension
E. Cheshmikhani, B. Peccerillo, A. Mondelli, S. Bartolini.
IEEE Access 10, 2022, pp. 120702-120713.
ACCESS

[12] A survey on hardware accelerators: Taxonomy, trends, challenges, and perspectives
B. Peccerillo, M. Mannino, A. Mondelli, S. Bartolini.
Journal of Systems Architecture, Volume 129, August 2022, 102561
JSA

[11] Applying Intel's oneAPI to a machine learning case study
P.A. Martínez, B. Peccerillo, S. Bartolini, J.M. García, G. Bernabé.
Concurrency and Computation Practice and Experience 34(13), 2022, e6917.
CCPE

[10] Performance portability in a real world application: PHAST applied to Caffe
P.A. Martínez, B. Peccerillo, S. Bartolini, J.M. García, G. Bernabé.
International Journal of High Performance Computing Applications 36(3), 2022, pp. 419-439.
IJHPCA

[9] Flexible task-DAG management in PHAST Library: Data-parallel tasks and orchestration support for heterogeneous systems
B. Peccerillo, S. Bartolini.
Concurrency and Computation Practice and Experience 34(2), 2022, e5842.
CCPE

2019

[8] Task-DAG Support in Single-Source PHAST Library: Enabling Flexible Assignment of Tasks to CPUs and GPUs in Heterogeneous Architectures
B. Peccerillo, S. Bartolini.
Proceedings of the 10th International Workshop on Programming Models and Applications for Multicores and Manycores (PMAM), Washington DC, United States, 2019, pp. 91-100.
PMAM

[7] Single-Source Library for Enabling Seamless Assignment of Data-parallel Task-DAGs to CPUs and GPUs in Heterogeneous Architectures
B. Peccerillo, S. Bartolini.
Proceedings of the 10th and 8th Workshop on Parallel Programming and Run-Time Management Techniques for Many-core Architectures and Design Tools and Architectures for Multicore Embedded Computing Platforms (PARMA-DITAM), Valencia, Spain, 2019, pp. 3:1-3:4.
PARMA-DITAM

[6] PHAST – A Portable High-Level Modern C++ Programming Library for GPUs and Multi-Cores
B. Peccerillo, S. Bartolini.
IEEE Transactions on Parallel and Distributed Systems 30(1), 2019, pp. 174-189.
TPDS

[5] Using Wearable Haptics for Thermal Discrimination in Virtual Reality Scenarios
G. Gioioso, M. Pozzi, M. Aurilio, B. Peccerillo, G. Spagnoletti, D. Prattichizzo
In: Kajimoto H., Lee D., Kim S.Y., Konyo M., Kyung K.U. (eds) Haptic Interaction. AsiaHaptics 2018. Lecture Notes in Electrical Engineering, vol 535. Springer, Singapore, 2019.
Book

[4] Parallel Bitsliced AES through PHAST: a Single-Source High-Performance Library for Multi-Cores and GPUs
B. Peccerillo, S. Bartolini, Ç. K. Koç.
Journal of Cryptographic Engineering 9(2), 2019, pp. 159-171.
J.Cr.En.

2018

[3] Parallel Programming in Cyber-Physical Systems
B. Peccerillo, S. Bartolini.
In: Ç. K. Koç (eds.) Cyber-Physical Systems Security, pp. 111-134, Springer International Publishing, Cham, 2018.
Book

2017

[2] PHAST Library – Enabling Single-Source and High Performance Code for GPUs and Multi-cores
B. Peccerillo, S. Bartolini.
2017 International Conference on High Performance Computing & Simulation (HPCS), Genova, Italy, 2017, pp. 715-718.
HPCS

[1] Procedimento per la Generazione Automatica di Codice di Calcolo Parallelo.
S. Bartolini, B. Peccerillo, inventori; Università degli Studi di Siena, titolare.
Italia brevetto IT 102017000082213. 2017 luglio 19.
Patent